During the product testing phase of semiconductor IC processing, packaged die are routinely put through operability testing by checking for shorts between adjacent pins, and also ensuring continuity of all pins. This quality control process is performed on all package styles, including those packages having single, dual and quad terminal positions.
This testing phase of ICs is a significant expense and a time consuming procedure that factors into the overall cost of producing the IC's.
Accordingly, reducing the test time required to check shorts between all adjacent pins, and also check the continuity of all pins for packages including those with single, dual and quad terminal positions is desired.